This invention relates a nonvolatile semiconductor memory device, and more particularly to a stacked gate structure of a memory cell transistor.
EEPROM is a type of nonvolatile semiconductor memory device capable of rewriting data electrically. Each memory cell in EEPROM is generally composed of an FETMOS transistor which has a floating gate between a control gate and a channel region and whose threshold voltage can be varied. EEPROMs are available in several types, depending on the way of connecting memory cell transistors. They include the NOR type, NAND type, AND type, and DINOR type.
FIG. 1A is a plan view of a memory cell array of a conventional NAND EEPROM memory cell array. FIG. 1B is a sectional view taken along a line 1Bxe2x80x941B of FIG. 1A.
As shown in FIGS. 1A and 1B, element isolating regions 102 are formed in a p-type silicon substrate 101. The element isolating regions 102 mark off one semiconductor active region 103 (element region) from another. The active regions 103 in the memory cell array have a parallel line pattern. The element isolating regions 102 are made of silicon dioxide. Although a high-concentration p+-type region called a channel stopper is usually formed below each element isolating region 102 in the substrate 101 to prevent the conductivity type directly under the element isolating region from being inverted, the channel stopper will be omitted in the present specification.
On the active regions 103, first gate insulating films 104 are formed thin enough to allow tunnel current to flow. The gate insulating films 104 are made of silicon dioxide (in the present specification, for the sake of convenience, the first gate insulating films 104 are referred to as tunnel oxide films).
On the tunnel oxide films 104, floating gates 105 are formed. The floating gates 105 are made of conductive polysilicon and function as charge storage layers that store charges. Each memory cell transistor is provided with one floating gate 105, which is isolated from the others. The threshold voltage of each memory cell transistor is adjusted according to the amount of electrons stored in the corresponding floating gate 105. Data is converted into the level of the threshold voltage and stored.
On the floating gates 105, a second gate insulating film 106 is formed. The second gate insulating film 106 is generally made of a stacked layer film called an ONO film (in the present specification, for convenience""s sake, the second gate insulating film 106 is referred to as the ONO film). In the stacked layer film, silicon dioxide, silicon nitride, and silicon dioxide are stacked in that order.
On the ONO film 106, control gates 107 are formed. The control gates 107 are made of conductive polysilicon and formed into continuous lines in the direction of the row in the memory cell array and function as word lines (in the specification, for convenience""s sake, the control gates 107 are referred to as the word lines).
The floating gates 105 and word lines 107 are formed by achieving consecutive etching using the same mask. As a result, the edges of the floating gates 105 align with those of the word lines 107 in the direction of the channel width (i.e., in the direction of the row in the figure). Hereinafter, the gate structure where the floating gate 105 and word line 107 are stacked is referred to as a stacked gate 108. With the stacked gates 108 and element isolating regions 102 as a mask, n-type source/drain regions 109 are formed by ion-implanting n-type impurities into the active regions 103.
In the memory cell array, the element isolating regions 102 are formed by local thermal oxidation of the silicon substrate 101. A typical example of this formation method is the LOCOS method.
FIGS. 2A and 2B are sectional views to help explain the procedure of the LOCOS method.
As shown in FIG. 2A, a buffer oxide film (silicon dioxide) 110 is formed on a silicon substrate 101. Then, the buffer oxide film excluding the regions in which the element isolating regions 102 are to be formed is covered with a silicon nitride film 111. In this state, using the nitride film 111 as a barrier to oxidation, the surface of the silicon substrate 101 is subjected heavily to thermal oxidation as shown in FIG. 2B. As a result, the element isolation regions 102 are formed.
In the LOCOS method, however, during oxidation, a wedge-shaped oxide film 112 called a bird""s beak develops along the interface between the silicon substrate 101 and the nitride film 111. This results in the conversion difference xe2x80x9cxcex94xe2x80x9d between the dimension xe2x80x9cWactualxe2x80x9d of the actually formed element isolating region 102 and the dimension xe2x80x9cWdesignxe2x80x9d of the element isolating region 102 in design.
As described above, because in the LOCOS method, the actual dimension xe2x80x9cWactualxe2x80x9d is larger than the design dimension xe2x80x9cWdesign,xe2x80x9d it is very difficult to form such microscopic element isolating regions 102 that, for example, the actual dimension xe2x80x9cWactualxe2x80x9d is equal to or less than 0.5 xcexcm.
Moreover, in the LOCOS method, it is difficult to form the element isolating regions 102 deep or thick in the silicon substrate 101. As the dimension xe2x80x9cWxe2x80x9d will be made smaller in the future, it will be much more difficult to form the element isolating regions 102 deep. The element isolating regions 102 formed in the memory cell array are exposed to an etching environment, especially when the stacked gates are processed. As a result, the thicknesses of the regions excluding the portions covered with the stacked gates decrease during the processing. The element isolating regions whose film thickness has been reduced have poorer insulation capabilities.
One of element isolating techniques to solve the above problem is a trench element isolating method of forming trenches in a silicon substrate and filling the trenches with insulating material.
FIG. 3A is a plan view of a conventional NAND EEPROM memory cell array using the trench element isolating method. FIG. 3B is a sectional view taken along a line 3Bxe2x80x943B of FIG. 3A. In these figures, the same parts as those in FIGS. 1A and 1B are indicated by the same reference symbols.
As shown in FIGS. 3A and 3B, trenches 121 are made in the substrate 101. The trenches 121 are filled with an insulating materiel 122. The insulating material 122 is made of silicon dioxide and functions as an element isolating region. Hereinafter, the insulating material is referred to as the trench element isolating region 122.
FIGS. 4A and 4B are sectional views to help explain the procedure of the trench element isolating method. As shown in FIG. 4A, the regions excluding the regions in which trench element isolating regions 122 are to form on the silicon substrate 101 are covered with a silicon nitride 123. In this state, with the nitride film 123 as a barrier to etching, the silicon substrate 101 is subjected to etching to form trenches 121.
Then, after silicon dioxide has been deposited on the entire surface of the silicon substrate 101, the deposited silicon dioxide is etched back by RIE techniques or CMP techniques and the trenches 121 are filled with silicon dioxide as shown in FIG. 4B. As a result, the trench element isolating regions 122 have been formed.
With such a trench element isolating method, the aforementioned conversion difference xe2x80x9cxcex94xe2x80x9d will not take place. Consequently, in the trench element isolating regions 122, the actual dimension xe2x80x9cWactualxe2x80x9d can be made 0.5 xcexcm or less.
Since the trenches 121 are formed inside the silicon substrate 101, the trench element isolating regions 122 can be formed deep in the substrate 101. This enables the trench element isolating regions to be made thicker than the LOCOS element isolating regions 102.
The trench element isolating method has realized thick element isolating regions 122 even in a memory cell array where microscopic line patterns are repeated. This widens a margin for a decrease in the film thickness caused during the processing of stacked gates, as compared with the LOCOS element isolating regions 102.
It is desirable, however, that a decrease in the thicknesses of the element isolating regions in the memory cell array should be suppressed as much as possible, regardless of whether they are of the LOCOS type or the trench type.
A decrease in the film thickness of the element isolating region in the memory cell array occurs not only during the processing of stacked gates but also the formation of high-withstand-voltage MOSFETs on the same substrate 101. In EEPROMs, a voltage higher than the power supply voltage is used to write or erase the data. In a transistor that generates or switches such a voltage, the gate oxide film has to be thicker than the tunnel oxide film 104 of the memory cell transistor from the viewpoint of securing the withstand voltage. A MOSFET that has a thick gate oxide film and is formed on the same substrate 101 is called a high-withstand-voltage MOSFET in the present specification.
In both the LOCOS method and the trench element isolating method, the tunnel oxide film 104 and thick gate oxide film have been formed after the formation of element isolating regions.
FIGS. 5A to 5C are sectional views to help explain the procedure for forming a conventional tunnel oxide film and thick gate oxide film, taking the trench element isolating method as an example.
As shown in FIG. 5A, after trench element isolating regions 122 have been formed, a silicon substrate 101 exposed at the surface of semiconductor active regions 103 are oxidized to form thick gate oxide films 131. The thick gate oxide films 131 are formed in a peripheral circuit region 132 in which a high-withstand-voltage MOSFET is to be formed in addition to the area of a memory cell array 133.
Then, as shown in FIG. 5B, the peripheral circuit region 132 is covered with, for example, photoresist 134. With the photoresist 134 as a mask, the thick gate oxide films 131 formed in the semiconductor active regions 103 in the memory cell array 133 are removed by wet etching. During the wet etching, because the element isolating regions 102 in the array 133 is made of silicon dioxide, they are etched at the same time. As a result, the surface of them are recessed more than the element isolating region 122 in the peripheral circuit region 132.
Thereafter, as shown in FIG. 5C, after the photoresist 134 has been removed, the silicon substrate 101 exposed at the active regions 103 in the array 133 is oxidized to form thin gate oxide films, or tunnel oxide films 104.
As described above, the conventional basic procedure is to form a MOSFET gate oxide film after the formation of the element isolating regions 122. According to the basic procedure, in an EEPROM where a thin gate oxide film is needed in the array 133 and a thick gate oxide film is needed in the peripheral circuit region 132, the surfaces of the element isolating regions 122 in the array 133 are recessed. As a result, their film thickness t133 is smaller than the film thickness t132 of the element isolating region 122 in the peripheral circuit region 132. Specifically, in the array 133, as the film thickness of the element isolating region 122 decreases from the thickness at the time when they were first formed, the margin gets narrower to another decrease in the film thickness during the processing of stacked gates.
An EEPROM to solve such a problem has been reported by, for example, Aridome et al. in IEDM, 1994. They have described what is called a self-alignment trench element isolating method, (IEDM Technical Digest 1994, pp. 61-64).
FIG. 6A is a plan view of a conventional NAND EEPROM memory cell array using the self-alignment trench element isolating method. FIG. 6B is a sectional view taken along a line 6Bxe2x80x946B of FIG. 6A. In these figure, the same parts as those in FIGS. 1A and 1B are indicated by the same reference symbols.
As shown in FIGS. 6A and 6B, trenches 141 are formed deep in a substrate 101, extending from the sidewalls of floating gates 105 inward. The trenches 141 are filled with insulating material. The insulating material is made of silicon dioxide and constitutes element isolating regions 142.
In a memory cell array using the self-alignment element isolating method, the element isolating regions 142 project from the surface of the semiconductor active regions 103 and their sidewalls are in contact with the sidewalls of the floating gates 105. Specifically, the element isolating regions 142 are formed after the formation of the tunnel oxide film 104 and floating gates 105.
FIGS. 7A to 7C are sectional views to help explain the self-alignment trench element isolating method and the procedure for forming a tunnel oxide film by this method.
As shown in FIG. 7A, a tunnel oxide film 104 and a conductive polysilicon film 143 from which floating gates 105 are to be made are formed in that order on a silicon substrate 101. Then, the area excluding the area in which element isolating regions 142 are to be formed is covered with a silicon nitride film 144.
Then, as shown in FIG. 7B, with the nitride film 144 as a barrier to etching, the conductive polysilicon film 143, tunnel oxide film 104, and silicon substrate 101 are etched in that order to form trenches 141.
Next, after silicon dioxide has been deposited on the entire surface of the silicon substrate 101, the deposited silicon dioxide is etched back by RIE or CMP techniques as shown in FIG. 7C to fill the trenches 141 with silicon dioxide. Thereafter, the nitride film 144 is removed to form self-alignment trench element isolating regions 142.
Unlike the conventional basic procedure, the basic procedure in the self-alignment trench element isolating method is to form a MOSFET gate oxide film before the formation of element isolating regions 142. Specifically, because the element isolating regions 102 are formed after the formation of the tunnel oxide film 104, a wet etching process in which the surfaces of the element isolating regions in the memory cell array are recessed during the formation of the tunnel oxide film 104 is basically absent.
Therefore, in the self-alignment trench element isolating regions 142, a stacked gate processing step can be started with the original film thickness in the memory cell array remaining almost unchanged. This increases a processing margin for a decrease in the film thickness caused during the processing of stacked gates, as compared with a memory cell array where elements are isolated by the conventional LOCOS method or trench element isolating method.
In a memory cell array where elements are isolated by the self-alignment trench element isolating method, however, the face of the floating gate 105 facing the word line 107 is basically the top surface of the floating gate 105 only. As a result, the capacitance C1 of the capacitor composed of a floating gate 105, a tunnel oxide film 104, and a channel (substrate 101) is almost the same as the capacitance C2 of the capacitor composed of a floating gate 105, an ONO film 106, and word line 107, except for the permittivity of the dielectric.
In EEPROMs, a write voltage VPP higher than the power supply is applied to a word line 107 in a data write operation or a data erase operation. Presently, the write voltage VPP tends to be lower. To make the write voltage VPP lower, it is better to make capacitance C2 larger than capacitance C1.
To realize this, the increase of the capacitance C2 has been considered by projecting the sidewalls of the floating gate 105 from the element isolating region 142. With this consideration, however, the exposure of the floating gate 105 results in a decrease in the film thickness of the element isolating region 142 in the memory cell array. This narrows the processing margin for the formation of stacked gates.
A first object of the present invention is to provide a nonvolatile semiconductor memory device having a structure which suppresses the decrease of the film thickness of element isolating regions in a memory cell array and is capable of increasing the capacitance between a floating gate and a word line with a high processing margin for the memory cell array.
A second object of the present invention is not only to achieve the first object but also to form memory cell transistors and select gate transistors while giving a sufficient processing margin to the STI regions in a memory cell array.
A third object of the present invention is to provide a nonvolatile semiconductor memory device capable of suppressing the decrease of the film thickness of element isolating regions in a portion in which select gate transistors are to be formed in a memory cell array where elements are isolated by self-alignment trench element separation.
To achieve the foregoing objects, a nonvolatile semiconductor memory device according to a first aspect of the present invention comprises: a semiconductor substrate; a plurality of element isolating regions provided in the semiconductor substrate; a plurality of first element regions, each of which is defined by two adjacent ones of the plurality of element isolating regions; and a plurality of memory cell transistors formed in the plurality of element regions, respectively, each of the plurality of memory cell transistors comprising: a first gate insulating film formed on the corresponding one of the plurality of first element regions, a floating gate electrode formed on the gate insulating film, a second gate insulating film formed on the floating gate electrode, and a control gate electrode formed on the second gate insulating film and connected in common to a specific number of ones of the plurality of memory cell transistors to serve as a word line, wherein the floating gate includes a first conductive member with side faces in contact with the side ends of the two adjacent one of the plurality of element isolating regions and a second conductive member electrically connected to the first conductive member and formed so as to bridge a gap between the two adjacent ones of the plurality of element isolating regions.
It is desirable that a top surface of the first conductive member is substantially flush with top surfaces of the two adjacent ones of the plurality of element isolating regions.
A position of a top surface of the first conductive member may be lower than top surfaces of the two adjacent ones of the plurality of element isolating regions, and the second conductive member may have a portion that contacts not only side faces of the two adjacent ones of the plurality of element isolating regions above the top surface of the first conductive member but also the top surfaces of the two adjacent ones of the plurality of element isolating regions.
The nonvolatile semiconductor memory device may further comprise a plurality of select transistors which are formed in the plurality of first element regions and select a specific one from the plurality of memory cell transistors, wherein each of the select transistors includes a third gate insulating film formed on the corresponding one of the plurality of first element regions, a first gate member formed on the third gate insulating film and in contact with side ends of the two adjacent ones of the plurality of element isolating regions, and a select gate electrode electrically connected to the first gate member and made of the same layer as that of the control gate electrode.
The first gate member may include a third conductive member made of the same layer as that of the first conductive member of each of the plurality of memory cell transistors, and a fourth conductive member electrically connected to the third conductive member and made of the same layer as that of the second conductive member of each of the plurality of memory cell transistors.
It is desirable that the same layer as that of the second gate insulating film is formed on the two adjacent ones of the plurality of element isolating regions that isolate each of the plurality of select transistors from each other.
It is desirable that each of the control gate electrode and the select gate electrode includes a first conductive layer that contacts the second gate insulating film and a second conductive layer that contacts the first conductive layer, the first conductive layer of the select gate electrode being formed on the same layer of the second gate insulating film above a corresponding one of the plurality of element isolating regions, and the second conductive layer of the select gate electrode being connected to the first gate member above a corresponding one of the plurality of first element regions.
The nonvolatile semiconductor memory device may further comprise: a second element region formed apart from the plurality of first element regions, and a peripheral circuit transistor formed in the second element region to drive the plurality of memory cell transistors, the peripheral circuit transistor including a fourth gate insulating film formed on the second element region and a gate electrode formed on the fourth gate insulating film, wherein the gate electrode of the peripheral circuit transistor includes a fifth conductive member made of the same layer as that of the first conductive member of each of the plurality of memory cell transistors, and a sixth conductive member electrically connected to the fifth conductive member and made of the same layer as that of the second conductive member of each of the plurality of memory cell transistors.
It is desirable that a difference in height between a surface of the first conductive member of the floating gate electrode and top surfaces of the two adjacent ones of the plurality of element isolating regions is substantially same throughout the plurality of memory cell transistors.
A thickness of the first conductive member may vary among the plurality of memory cell transistors.
Both of side faces of the second conductive member on the two adjacent ones of the plurality of element isolating regions may be tapered.
Each of the plurality of first element regions is formed in a line-form and plural of the plurality of memory cell transistors are formed in one of the plurality of first element regions, each of the plurality of memory cell transistors having a source and a drain region formed so as to sandwich the floating gate electrode in one of the plurality of first element regions and sharing one of the source and the drain region with adjacent one of the plurality of memory cell transistors.
A nonvolatile semiconductor memory device according to a second aspect of the present invention comprises: a semiconductor substrate; a plurality of element isolating regions provided in the semiconductor substrate; a plurality of element regions, each being sandwiched between two adjacent ones of the plurality of element isolating regions; and a plurality of memory cell transistors and a plurality of select transistors formed in the plurality of element regions, wherein each of the plurality of memory cell transistors includes a first gate insulating film formed on a corresponding one of the plurality of element regions, a floating gate electrode formed on the first gate insulating film, correspondingly to the plurality of element regions, a second gate insulating film formed on the floating gate electrode, and a control gate electrode formed on the second gate insulating film, and each of the plurality of select transistors includes a third gate insulating film formed on a corresponding one of the plurality of element regions, a gate member formed on the third gate insulating film, correspondingly to one of the plurality of element regions, and a select gate electrode formed on the gate member and electrically connected to the gate member.
It is desirable that each of the control gate electrode and the select gate electrode includes a first conductive layer that contacts the second gate insulating film and a second conductive layer that contacts the first conductive layer, the first conductive layer of the select gate electrode being formed on the same layer as that of the second gate insulating film above the plurality of element isolating regions, and the second conductive layer of the select gate electrode being connected to the gate member above the plurality of element regions.
A nonvolatile semiconductor memory device according to a third aspect of the present invention comprises: a semiconductor substrate; a plurality of element isolating regions provided in the semiconductor substrate; a plurality of element regions, each being sandwiched between two adjacent ones of the plurality of element isolating regions; and a plurality of memory cell transistors and a plurality of select transistors formed in the plurality of element regions, wherein each of the plurality of memory cell transistors includes a first gate insulating film formed on a corresponding one of the plurality of element regions, a floating gate electrode which is formed on the first gate insulating film and whose side ends contact two adjacent ones of the plurality of element isolating regions, a second gate insulating film formed on the floating gate electrode, and a control gate electrode which is formed on the second gate insulating film and extends over the two adjacent ones of the plurality of element isolating regions, and each of the plurality of select transistors includes a third gate insulating film formed on a corresponding one of the plurality of element regions, a gate member which is formed on the third gate insulating film and whose side ends contact the two adjacent ones of the plurality of element isolating regions, and a select gate electrode which is formed on the gate member and electrically connected to the gate member and extends over the two adjacent ones of the plurality of element isolating regions, and a thickness of a corresponding one of the plurality of element isolating regions under the select gate electrode is essentially larger than a thickness of the corresponding one of the plurality of element isolating regions under the control gate electrode.
It is desirable that the nonvolatile semiconductor memory device further comprises a first region that is formed in each of the plurality of element regions and functions as one of a source and a drain region of each of the plurality of select transistors, a second region that is formed in each of the plurality of element regions and functions as one of the source and the drain region of each of the plurality of memory cell transistors, and a third region that is formed in each of the plurality of element regions and functions as the other of the source and the drain region for one of the plurality of select transistors and one of the plurality of memory cell transistors adjacent to the one of the plurality of select transistors and is shared by the one of the plurality of select transistors and the one of the plurality of memory cell transistors, wherein a distance from a top surface of the gate member of each of the plurality of select transistors to a top surface of a portion isolating the first region in the plurality of element isolating regions is equal to or smaller than a distance from a top surface of the floating gate electrode of each of the plurality of memory cell transistors to a top surface of a portion isolating the second region in the plurality of element isolating regions.
It is desirable that a film thickness of a portion isolating the first region in the plurality of element isolating regions is equal to or larger than a film thickness of a portion isolating the second region in the element isolating regions.
It is desirable that a film thickness of a portion corresponding to each of the plurality of element isolating regions under the select gate electrode is equal to or larger than a film thickness of a portion isolating the first region in the plurality of element isolating regions.
It is desirable that a film thickness of a part of a portion corresponding to each of the plurality of element isolating regions under the select gate electrode is substantially equal to a film thickness of a portion isolating the first region in the plurality of element isolating regions and smaller than a film thickness of a remaining part of the portion corresponding to each of the element isolating regions under the select gate electrode.
It is desirable that a portion isolating the third region in the plurality of element isolating regions has a step.
With the present invention, it is possible to provide a nonvolatile semiconductor memory device which is capable of suppressing a decrease in the film thickness of the element isolating regions in a memory cell array while securing a substantial processing margin for the memory cell array and which has a structure capable of increasing the capacitance between the floating gate and the word line. It is also possible to provide a method of manufacturing such nonvolatile semiconductor memory devices.
Furthermore, with the present invention, it is possible to provide a nonvolatile semiconductor memory device which not only produces the above effect but also is capable of forming memory cell transistors and select gate transistors while giving a sufficient processing margin to the STI regions in a memory cell array.
Still furthermore, with the present invention, it is possible to provide a nonvolatile semiconductor memory device which is capable of suppressing a decrease in the film thickness of the element isolating regions in the portion where select gate transistors are formed in a memory cell array whose elements are isolated by self-alignment trench element isolation. It is also possible to provide a method of manufacturing such nonvolatile semiconductor memory devices.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinbefore.